Field of the Invention
The present invention relates to a processing apparatus and a method of the same. 2. Description of the Related Art
A processing apparatus which receives as its inputs positive binary data A, B, and C and performs an operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d, is known in the art.
Below, an explanation will be made of a processing apparatus of the related for performing the operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d.
FIG. 6 is a view of the configuration of the processing apparatus of the related for performing the operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d.
As shown in FIG. 6, the processing apparatus 1 has a subtracter 2 and a multiplier 3 and performs the operations xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d by using the 4-bit data A, B, and C.
The processing apparatus 1, for example, performs the subtraction of the 4-bit data A and the 4-bit data B at the subtracter 2 and the multiplication of the signed 5-bit subtraction result Y and the 5-bit data C with a most significant bit (MSB) having a logical value xe2x80x9c0xe2x80x9d due to code expansion at the multiplier 3. Then, the multiplication result of the multiplier 3 becomes the result of the operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d.
As the subtracter 2, for example, as shown In FIG. 7. a ripple carry type adder comprised of full adders (FA) 100, 101, 102, and 103 connected in series, is used.
In this subtracter 2, xe2x80x9c1xe2x80x9d for finding a complement of 2 is Input to a Ci (Carry In) terminal of the full adder 101 performing the operation corresponding to the least significant bit (LSB). Further, the bit data A0 to A3 of the data A are Input to the full adders 100 to 103 and the bit data B0 to B3 of the data B are Input via inverters 110 to 113. Then, bit data Y0 to Y3 of the 4-bit result Y are output from s terminals of the full adders 100 to 103 and bit data Y4 indicating the sign of the subtraction result Y Is output from a CO (Carry Out) terminal of the full adder 103.
Note that, as the full adders 101 to 103, as shown In FIG. 8, use is made of a general full adder constituted by combining AND circuits 151, and 152, OR and 172. At the full adders 101 to 103, bit data input through an in1 terminal, in2 terminal, and Ci (Carry in ) terminal are added, the carry of the addition result Is output from the CO (Carry out) terminal, and sum data Is output from the S terminal.
Next, an explanation will be made of the configuration of the multiplier 3 shown In FIG. 6.
FIG. 9 Is a view for explaining a complement multiplication of 2 according to the Baugh Wooly method adopted by the multiplier 3.
A FIG. 10 is a view of the configuration of the multiplier 3 performing the complement multiplication of 2 shown in FIG. 9.
As shown in FIG. 10, the multiplier 3 has a partial product adder circuit 20 and a final stage adder circuit 30.
The partial product adder circuit 20 adopts the Wallace-tree method and has AND circuits 210 to 2124, full adders 221 to 2213, half adders 231 to 233, and inverter circuits 241 to 2411.
Further, the final adder circuit 30 adopts the Ripple Carry method and has full adders 2214 to 2219 and half adders 234 and 235.
Here, the full adders 2214 to 2219 have the configuration shown in FIG. 8 mentioned above. Further, as the half adders 231 to 233, as shown in FIG. 11, provision is made of an AND circuit 153 and an XOR circuit 173, data input through the in terminal and the in2 terminal are added, the carry of the related addition result is output from the CO (Carry Out) terminal, and the sum data is output from the S terminal.
At the multiplier 3, the AND circuits 211 to 2124 of the partial product adder circuit 20 use the bit data Y0, Y1, Y2, Y3, and Y4 of the subtraction result Y from the subtracter 2 and the bit data C0, C1, C2, C3, and 0 with an MSB having the logical value xe2x80x9c0xe2x80x9d due to code expansion for the partial products shown in FIG. 9. Then, the partial products are added at the full adders 221 to 2219 and the half adders 231 to 235 of the partial product adder circuit 20 and the final stage adder circuit 30 including a carry from a lower digit for every digit. By this, sum data output from the output terminal of the AND circuit 210 and s terminals of the half adders 231 and 234, the full adders 2214, 2215, 2216, 2217, 2218, and 2219, and the half adder 235 become bit data S0, S1, S2, S3, S4, S5, S6, S7, S8, and S9 of the 10-bit result S.
Summarizing the problem to be solved by the invention, in the processing apparatus 1 of the related art mentioned above, as shown in FIG. 7 and FIG. 10, there is a disadvantage that there are the full adders 100 to 103, AND circuits 210 to 2124, full adders 221 to 2219, half adders 231 to 225, and inverter circuits 241 to 2411 and the size of the circuit becomes large.
Namely, in the processing apparatus 1, as shown in FIG. 1, in order to perform the subtraction at the subtracter 2, when using 4-bit data A and B, the result thereof becomes 5 bits, including the sign bit. As a result, at the multiplier 3, it is necessary to perform the multiplication of 5 bits and the size of the circuit becomes large.
Further, in the processing apparatus 1 of the related art mentioned above, the critical path of the operation becomes the full adders 100 to 103, half adder 234, full adders 2214, 2215, 2216, 2217, 2218, and 2219, and the half adder 235, so there is a disadvantage that the processing time becomes long.
An object of the present invention is to provide a processing apparatus capable of reducing the size of the circuit performing the operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d.
Another object of the present invention is to provide a processing apparatus capable of shortening the processing time of the operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d.
According to a first aspect of the present invention, there is provided a processing apparatus for calculating xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d where the bit data A is constituted by the n-bit data of Ai (i=0, 1, . . . nxe2x88x921), the bit data B is constituted by the n-bit data of Bi (i=0, 1, . . . nxe2x88x921), and the bit data C is constituted by the n-bit data of Cj (j=0, 1, . . . nxe2x88x921), said processing apparatus comprising: a bit data selecting means for receiving as input the bit data Ai, Bi, and Cj, and outputting the bit data Ai when Cj equals to a first logical value or the bit data Bi when data Cj equals to a second logical value in response to data Cj with respect to all combinations of the natural numbers i and J and an adding means for adding the bit data output from the bit data selecting means to the (i+j)th bit for each bit of all combinations of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.
The processing apparatus of the present invention performs the operation xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d based on the following equation (1):                     S        =                              (                                          ∑                                  j                  =                  0                                                  j                  =                                      n                    -                    1                                                              ⁢                                                ∑                                      i                    =                    0                                                        i                    =                                          n                      -                      1                                                                      ⁢                                  ·                                      (                                                                                            A                          j                                                ·                                                  C                          j                                                                    |                                                                        B                          i                                                ·                                                                              C                            _                                                    j                                                                                      )                                                                        )                    -                                    2              n                        xc3x97            B                    +          B                                    (        1        )            
That is, in the processing apparatus of the present invention, each of the plurality of bit data selecting means outputs the bit data Ai when the input Cj is the logical value xe2x80x9c1xe2x80x9d and outputs the bit data Bi when Cj is the logical value xe2x80x9c0xe2x80x9d among the input bit data Ai and Bi.
Next, the adding means adds the bit data output from the bit data selecting means to the (i+j)th bit by adding for each bit the bit data output from the bit data selecting means, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, the data B, and the carry data carried from a lower bit.
Preferably, it further provides with an inverted value generating means for inverting the bit data B0, B1, . . . , Bi, . . . , Bnxe2x88x922, and Bnxe2x88x921 to find the bit data B0xe2x88x92, B1xe2x88x92, . . . , Bixe2x88x92, . . . , Bnxe2x88x922xe2x88x92, and Bnxe2x88x921xe2x88x92; the adding means respectively adds the bit data B1xe2x88x92, . . . , Bixe2x88x92, . . . , Bnxe2x88x921xe2x88x92, found by the inverted value generating means to the (n+1)th, . . . , (n+i)th, . . . , (2nxe2x88x921)th bits and adds the bit data B0xe2x88x92 and the logical value xe2x80x9c1xe2x80x9d to the n-th bit.
Preferably, the adding means adds the bit data B0, B1, . . . , Bi, . . . , Bnxe2x88x922, and Bnxe2x88x921 of the data B to the 0th, 1st, . . . , i-th, . . . , (nxe2x88x922)th, and (nxe2x88x921)th bits.
Preferably, the adding means outputs as the result of the addition (2n+1)bit data comprised of the bit data S0, S1, . . . , S2nxe2x88x921 and S2n and the bit data S2n shows the sign value.
Preferably, the bit data selecting means each has a first transmission gate which becomes conductive when the input bit data Ci is the logical value xe2x80x9c1xe2x80x9d and a second transmission gate which becomes conductive when the input bit data Ci is the logical value xe2x80x9c0xe2x80x9d.
According to a second aspect of the present invention, there is provided a processing method for calculating xe2x80x9c(Axe2x88x92B)xc3x97Cxe2x80x9d where the bit data A is constituted by the n-bit data of Ai (i=0, 1, . . . nxe2x88x921), the bit data B is constituted by the n-bit data of Bi (i=0, 1, . . . nxe2x88x921), and the bit data C is constituted by the n-bit data of Cj (j=0, 1, . . . nxe2x88x921), said processing method comprising the steps of: performing processing for receiving as input the bit data Ai, Bi, and Cj, selecting the bit data Ai when data Cj equals to a first logical value or Bi when data Cj equals to a second logical value in response to the bit data Cj with respect to all combinations of the natural numbers i and j and adding the selected bit data to the (i+j)th bit for each bit of all combination of i and j, the data obtained by shifting the data of the complement of 2 of the data B by exactly n number of bits toward the most significant bit, and the data B.